The present application describes systems and techniques relating to marking of semiconductor wafers, for example, marking silicon wafers with crystallographic orientation marks.
Silicon wafers are commonly manufactured for the semiconductor industry to standard form factors and at times with laser written identification numbers. These conventions and standards have allowed the Microelectronics and Integrated Circuits industry to efficiently expand reliably over a broad base of customer markets.
Moreover, semiconductor wafers are typically manufactured from individual crystals, which each have a particular crystal lattice orientation. Generally, the crystallographic orientation of a semiconductor wafer can have significant impact on the effectiveness of certain methods of processing the semiconductor wafer and on the performance of transistors, or other devices, formed in the semiconductor wafer. Typically, semiconductor wafers are manufactured to have a particular crystallographic orientation at their surface, and a wafer flat to aid in alignment of the wafer during various processing operations.
In one aspect, a method of marking a semiconductor wafer includes identifying a crystallographic orientation of a semiconductor wafer, precisely aligning the semiconductor wafer, and marking the semiconductor wafer with an embedded crystallographic-orientation alignment mark. The semiconductor wafer may be a silicon wafer, and the marking may be performed using abrasive impact removal techniques, such as by forcibly directing a carrier medium containing an abrasive material through a stencil to create the crystallographic-orientation alignment mark on the silicon wafer.
The precision alignment and the marking may be performed repeatedly as part of an automated machining process, including appropriate control systems as needed. The precision alignment may be performed using a wafer flat and a precision machined metal alignment stop. The embedded crystallographic-orientation alignment mark may encode more a than one piece of information regarding crystallographic-orientation features of the semiconductor wafer. The embedded crystallographic-orientation alignment mark may be one or more surfaces defining a line in the silicon wafer.
The embedded crystallographic-orientation alignment mark may encode information in various ways. For example, in the case of a line on the semiconductor wafer, information may be encoded in the line""s orientation, length, or depth. Moreover, the embedded crystallographic orientation alignment mark may pass entirely through the semiconductor substrate.
In another aspect, a semiconductor wafer is composed of a substrate having a top surface and a bottom surface, the top surface defining a top plane with a top perimeter and the bottom surface defining a bottom plane with a bottom perimeter, and the wafer includes a surface within the top perimeter that breaks the top plane and stores information regarding a crystallographic orientation of the semiconductor wafer. Alternatively, the crystallographic-orientation information storing surface is within the bottom perimeter and breaks the bottom plane.
The crystallographic-orientation information storing surface may store multiple types of information regarding crystallographic-orientation features of the semiconductor substrate. The semiconductor wafer may also have a wafer flat. The crystallographic-orientation information storing surface may define a line in the semiconductor substrate, and information may be encoded in the line""s orientation, length or depth. Finally, the crystallographic-orientation information storing surface may break both the top and bottom planes to define a hole in the semiconductor wafer.
In another aspect, a method of manufacturing semiconductor wafers includes cutting a crystal ingot comprising a semiconductor material into thin wafers, identifying a crystallographic orientation of one or more semiconductor wafers from the thin wafers, and adding a crystallographic-orientation alignment mark to each of the semiconductor wafers before distribution of the semiconductor wafers to integrated circuit manufacturers. The process of adding of the crystallographic-orientation alignment mark to each semiconductor wafer may be performed in many different manners, including, adding a wafer flat to the semiconductor wafer, aligning the semiconductor wafer against a precision machined metal alignment stop, pressing the semiconductor wafer against the precision machined metal alignment stop, and forcibly directing a carrier medium including an abrasive material through a stencil to create the crystallographic-orientation alignment mark on the semiconductor wafer in a shape corresponding to a design in the stencil.
When semiconductor wafers are manufactured with an additional marking that precisely defines the crystallographic orientation of the wafer, the wafers may be sold as an added value product, reducing the time needed to fabricate integrated circuit components during later processing. The precise alignment mark may be used during lithography to precisely align the invisible atomic arrangement of the atoms in the wafer to physical features on the wafer. This ability may be of particular importance to the micromachining, microelectromechanical device, and sensor device industries.
Moreover, this ability may be highly beneficial in orientating micromachined features via a photolithographic process to the arrangement of atoms in the semiconductor material (e.g., silicon). For example, when etching a semiconductor wafer, precise alignment of the wafer is typically critical, and having a precise crystallographic alignment mark in proximity to the etching area may provide significant aid in proper masking alignment.